Paper Presented at IEDM 2018 Describes Breakthroughs in Six Process Steps
Leti, a research institute at CEA Tech, has reported breakthroughs in six 3D-sequential-integration process steps that previously were considered showstoppers in terms of manufacturability, reliability, performance or cost.
- Low-resistance poly-Si gate for the top field-effect transistors (FETs)
- Full LT RSD (low temperature raised source and drain) epitaxy, including surface preparation
- Stable bonding above ultra low-k (ULK)
- Stability of intermediate back end of line (iBEOL) between tiers with standard ULK/Cu technology
- Efficient contamination containment for wafers with Cu/ULK iBEOL, enabling their re-introduction in front end of line (FEOL) for top FET processing, and
- Smart CutTM process above a CMOS wafer.