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    Cobalt solutions best helper for 7nm node: Q&A with Applied Materials executive Jonathan Bakke

    Julian Ho, Taipei; Willis Ke, DIGITIMES

    While Taiwan Semiconductor Manufacturing Company (TSMC) and Samsung are entering the 7nm process era, the latest cobalt-based process solutions rolled out by Applied Materials following over 10 years of development will be the best helper for 7nm foundry node, as they can help increase, by 5-15%, the performance of AI and high-performance computing (HPC) chips fabricated on 7nm node, according to Jonathan Bakke, global product manager for Contact and Middle of Line Products in the Metal Deposition Products Business Unit at the US-based leader in semiconductor materials engineering solutions.

    Bakke told Digitimes in a recent interview that Applied Materials’ cobalt-based solutions represent a major breakthrough in materials engineering to accelerate the chip performance in the big data and AI era, adding that the company has started delivering the solutions to major customers.

    Q: Why do you adopt the cobalt metal in material engineering solutions and how will it influence the semiconductor industry?

    A: In fact, the appearance of the cobalt material is quite an exciting thing. Since IBM replaced aluminum with copper in 1997, the materials application field has seen little change, and therefore adopting cobalt has become a new major metal change to transistor contact and interconnect in 20 years.

    We can see semiconductor applications roughly divided into three major stages: first for PC and internet application, then for mobile devices and social networks, and now for AI, big data, and automation. Industry players are all focusing on the third stage, but the Moore’s Law has reached its physical limits, so Applied Materials has managed to adjust materials to extend the Moore’s Law and better meet the PPAC requirements of chips.

    Q: What are the chip’s PPAC requirements ?

    A: The PPAC requirements entail that chips can be volume produced using x-nm process nodes to achieve higher ‘Performance’, lower ‘Power’ consumption, smaller ‘Area’ and lower ‘Cost’. With the advent of the AI and big data era, such requirements are casting challenges for the traditional Moore’s Law.

    Let us briefly review the evolutions of mobile devices in the past 30 years. In terms of performance, mobile devices have seen exponential growth, in that they can function as not only phones, but also web access and gaming devices. In power consumption, many other needs than phone calls have to be covered. Meanwhile, IC scaling has kept improving. Apple’s smartphone processors, for instance, have become tinnier and tinnier when evolving from A5 to A11, with the performance increasing 10-folds when progressing from A8 to A11 alone. Cost-wise, a mobile phone was sold for around US$4,000 in early years, but the price has fallen sharply to about US$600. In bracing for the arrival of the AI and big data era, the introduction of new materials and material engineering solutions is increasingly crucial for the PPAC requirements of chips to be fulfilled.

    Q: What about the evolutions in wafer fabrication equipment in the three main semiconductor application stages mentioned earlier?

    A: In the PC era, planar transistor structure was the mainstay, and chips’ PPAC requirements could be easily met without materials integration or lithography adoption. And our customers started to incorporate self-aligned double patterning (SADP) and self-aligned quadruple pattering (SAQP) technologies in the mobile device era, and now even have moved to adopt EUV (extreme ultraviolet) lithography technology. Of course, transistor structures must be adjusted along with the advancement of fabrication process nodes to achieve the PPAC effects of chips, with FinFET, for instance, able to enhance chip performance.

    Intel started using tri-gate FinFET devices at the 22nm in 2011, and now the gate-all-round (GAA) FET process is also available. The FinFET and GAA FET process technologies alone, however, are not sufficient enough to upgrade the performance of chips, but material engineering breakthroughs will play a crucial role in meeting PPAC requirements of chips needed in the AI era.

    Q: How do you see the advantages of cobalt adopted as a conducting material in the AI era?

    A: More and more HPC chips will be needed in the AI era, and so will be new materials. Today, materials such as tungsten and copper are no longer scalable beyond the 10nm foundry node because their electrical performance has reached physical limits for transistor contacts and local interconnects. This has created a major bottleneck in achieving the full performance potential of FinFET transistors. Cobalt can remove this bottleneck but also requires a change in process system strategy. As the industry scales structure to extreme dimensions, the materials behave differently and must be systematically engineered at the atomic scale, often under vacuum.

    After figuring out some parameters, we have found cobalt outperforming tungsten, aluminum and copper in the critical dimensions of under 20nm, showing lower resistance and variability, better gap-fill capability and higher reliability. Of the three traditional materials, only copper still performs well in the critical dimensions of over 30nm process.

    Q: How do you assess the competitive advantages of Applied Materials in the cobalt-based material engineering solutions? What about the material cost of cobalt?

    A: Applied Materials has been pursuing integrated material engineering solutions to best serve customer needs. To enable the use of cobalt as a new conducting material in the transistor contact and interconnect, our company has offered end-to-end product portfolios by combining several materials engineering steps – pre-clean, PVD, ALD, and CVD – on the Endura platform. Moreover, our company has also defined an integrated cobalt suite that includes anneal on the Producer platform, planarization on the Reflexion LK Prime CMP platform, and e-beam inspection on the Provision platform. Customers can use this proven Integrated Materials Solution to speed time-to-market and increase chip performance at the 7nm foundry node and beyond.

    Cobalt as a conducting material is especially suitable for advanced 7nm process and beyond, and we believe that as long as foundry houses enter the 7nm process, they will surely need the cobalt material to break the bottleneck in transistor contact and interconnect.

    As far as pure material cost is concerned, cobalt is three times more expensive than tungsten, but it remains inconvenient for us to comment on the actual cost that also involves the cost of collaborative R&D with customers.

    In fact, Applied Materials is the only semiconductor equipment supplier with most comprehensive technological capabilities to explore the broadest portfolio of solutions, and we are sure that volume production of chips fabricated with our latest cobalt-based solutions may be seen probably in September 2018.