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    Going to Extremes in Support of Moore’s Law


    pmd1365_article_img_going_to_extremes_in_support_of_moores_law.jpgBy Ryan Lopez

    In recent years, speculation among technologists has been rife that Moore’s Law, the guiding precept in computer engineering that has dominated development for five decades, will be eclipsed in the not-too-distant future.

    Technologists contend that the laws of physics spell an end to the seminal development trend first observed in 1965 by Intel co-founder Gordon Moore: The number of transistors housed on a semiconductor double every 18 months as the cost for producing them has halved over that timeframe.

    In short, and economics aside, there simply isn’t enough real estate on a piece of silicon on which to etch ever-more integrated circuits.

    The Race to Atomic Level
    Enter the world’s chip makers, who are building entire systems on chips (SoCs) as they race to atomic level in an effort to deliver greater processing capacities in finite space.

    Late last month, Silicon Valley chip architect Arm announced that it would work with the chip-making subsidiary of Korean device maker Samsung Foundry to embed new functionality onto 7 nanometer (nm) nodes. The nodes are roughly the length of an individual transistor and more than 100 million can be packed into a square millimeter of silicon.

    The company’s MagnetoResistive Random Access Memory compiler will grace 7nm chips that the Samsung foundry expects to begin producing in volume later this year.

    Built using extreme ultraviolet lithography (EUV) in which 13.5nm wavelengths of light are used to imprint patterns onto the layers of pure silicon that make up each chip, the architecture permits designers to scale memory for use-case complexity, including the variety of low-power sensors and other devices that comprise the Internet of Things.

    Manufacturers Hustle the ‘Chiplet’
    Taiwan-based maker TSMC, which in April began volume production of 7nm chips, is using deep ultraviolet technology (DUV) to build SoCs. DUV uses longer wavelengths (193nm) to print circuit patterns, enabling the world’s largest contract manufacturer to employ the same machines it uses to produce the 10nm chips that the shorter standard is replacing.

    TMSC’s rush to market necessitates that customers use multi-pattern circuit designs for each use case, a trade-off reflected in longer production cycles and higher costs. The company, along with US subcontractor GlobalFoundries , is scaling up to supply branded maker AMD with 7nm chips for gaming applications and expects to implement EUV in 2019.

    The higher densities permitted by today’s shorter transistor lengths – which have fallen more than a thousand-fold from the 10-micron standard used in 1971 – increase frequencies and lower power consumption. They also permit the construction of SoCs, like the one Qualcomm is making for Samsung’s Galaxy smartphones, complete with memory and input/output ports that support the processing core.

    In that regard, EUV, which employs only seven steps in manufacture compared with DUV’s 34, is a process revolution – one that promises to help shorten transistor lengths still further.

    IBM is using the technology to good effect, having produced nodes at 7nm and 5nm over the course of the last 12 months. And, TMSC, which also produces chips for Apple, Nvidia and Qualcomm, is said to be working on 3nm fabrication, which Moore’s Law dictates should be the common standard by 2022.

    Stackable Solutions on Existing Architecture
    However, not all chip makers are adopting next-generation lithography to boost processing power. Intel, which Moore helped to launch in 1968, is touting software solutions and parallel processing on the 14nm standard that it introduced in 2014.

    Intel says that 18 cores can fit on those chips, replicating densities on the shorter standards, and that clustering can achieve processing capabilities that exceed the pace envisioned by the company’s founder. Like TMSC, the company is simultaneously developing architectures that stack wafers constructed on differing standards in a single chip.

    While critics and competitors point to a failure to deliver even a 10nm chip on schedule – Intel says delivery is unlikely before the end of the year – the company appears wise to let next-generation processes settle into the industry standard.

    Whatever the case – and the reported $120 million price tag for an EUV foundry (easily affordable given Intel’s $16 billion earnings in Q1 2018) – the adoption of leading-edge manufacturing techniques reflect less an end to Moore’s Law and more an architectural revision. And, go figure, Moore predicted that, too.