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    Inside FD-SOI And Scaling

    Inside FD-SOI And Scaling

    GlobalFoundries’ CTO opens up on FD-SOI, 7nm finFETs, and what’s next in scaling.

    Gary Patton, chief technology officer at GlobalFoundries, sat down with Semiconductor Engineering to discuss FD-SOI, IC scaling, process technology and other topics. What follows are excerpts of that conversation.

    SE: In logic, GlobalFoundries is shipping 14nm finFETs with 7nm in the works. The company is also readying 22nm FD-SOI technology with 12nm FD-SOI in R&D. Why develop both finFETs and FD-SOI?

    Patton: We are providing our customers with technology that’s really optimized for their applications. We are not trying to fit everybody from high-end servers to battery-powered devices into one technology flavor.

    SE: There is some confusion where FD-SOI and finFETs compete in the market. Can you elaborate?

    Patton: I am a big fan of finFETs. I spend a lot of my time on 7nm. We are trying to get that ready for customer tape-outs early next year. It’s a great technology if you are focused on performance. If you are making large chips and you have a lot of wire capacitance, you love the drive current of a finFET device. But if you are making smaller chips, where the gate capacitance is a bigger issue, then the finFET has a little bit of a disadvantage. Also, it’s a much more complex process. Not everybody is making a million wafers for their products. It’s a more expensive process. And it has more complexity with double-, triple- and quadruple- pattering, as well as the complexities with RF and analog design in a finFET device.

    SE: What about FD-SOI?

    Patton: FD-SOI is really a technology optimized for the low-cost IoT, battery-powered, low-end mobile and automotive applications.

    SE: Do you push one technology over another?

    Patton: We’re agnostic. We’re not telling customers that you have to do finFETs or FD-SOI. We want customers to use the technology that fits their application.

    SE: Who are the early adopters for 22nm FD-SOI?

    Patton: Automotive is definitely one of the strong ones. The camera space is another, and some of the battery-powered IoT.

    SE: What’s happening in automotive?

    Patton: Certain applications in automotive are better optimized for FD-SOI like radar. Other applications may use finFETs. So we are actually going through automotive qualification in our Malta fab for 14nm. Again, the auto makers can choose.

    SE: GlobalFoundries has announced 22nm FD-SOI with plans to add more capabilities to the technology, right?

    Patton: The base technology is done. The base IP development is done. And now, we are working on the extensions. We believe one of the killer applications for this is to be able to do a single-chip solution for the IoT space. That’s RF and everything.

    SE: What else are you doing with FD-SOI?

    Patton: There’s embedded memory. We have MRAM, which we will bring in. And, of course, we have 12nm work going on.

    SE: IP is key for FD-SOI, right?

    Patton: The yields are basically at 28nm yields. Performance is above our targets. It’s fully qualified. Now the focus is continuing to build up the IPecosystem. We have the foundation and application IP in place.

    SE: 22nm is one of the new battlegrounds in the foundry business. First, GlobalFoundries rolled out 22nm FD-SOI. Then, TSMC introduced a 22nm bulk process. And Intel introduced a new version of its 22nm finFET technology. What’s happening here? And how does 22nm FD-SOI stack up against the other technologies?

    Patton: All of a sudden, 22nm has become a big battleground. Certainly, if you are looking at anything with RF requirements, I wouldn’t even put finFET in the game, because finFETs don’t have the same RF capabilities that a planar device has. So it becomes bulk versus FD-SOI. And FD-SOI is really optimized for this low-power space. With bulk, you don’t have the ability to do body-bias.

    Fig. 1: Bulk CMOS vs FD-SOI. Source: GlobalFoundries

    Fig. 2: 7nm finFET. Source: GlobalFoundries

    SE: There is a perception that only a few customers have adopted FD-SOI. What are the challenges of getting more adoption for FD-SOI?

    Patton: We’ve worked with lead customers on FD-SOI and they now understand the issues. First, there was the history or concerns about execution. We are well past that. People understand 22nm. It’s solid technology and it’s yielding very well. We’ve executed what we’ve planned. We knew IP was going to be critical, because FD-SOI is new and different for people. So we’ve been investing from the beginning on the IP ecosystem. Our initial partner was Invecas to help build up the foundational IP. Since then, we’ve made a big increase and investment in all of the IP around the technology.

    SE: What else?

    Patton: By the way, there’s multi-sourcing. We have a fab coming up in Chengdu, China. Also, we know China will be a big market for FD-SOI. That’s been pretty clear from the conversions we’ve had with customers in China. So, we will have two big factories for FD-SOI—Dresden and Chengdu.

    SE: Some analysts say you need more IC design resources to make chips around FD-SOI, as compared to bulk CMOS. Is that the case?

    Patton: That’s some of the FUD (fear, uncertainty and doubt) spread by our competitors. We have programs to help teach our customers how to use back-bias. A number of them are starting out without back-bias. They get that under their belt, and then they can take the product to the next level by using back-bias. Some of our ecosystem partners are putting the tools in place, so that it’s fairly easy to design with back-bias. You do have to think about how you want to architect the system. That’s where they provide their value in terms of differentiation and figuring out how they want to leverage this thing called body-bias at a circuit, block or chip level.

    SE: Why do designers need back-bias for FD-SOI?

    Patton: You can apply that in a couple different ways. You can tune the voltage on a given chip. So you can tighten up the distributions of the product. Or you can take a block and throttle it up or down. I have an example in some of the presentations I give of a chip, where you have a block which is always on. And it’s a processor that is monitoring what’s going on in the environment. And you use the ultra-low leakage devices in that area. And the rest of it has the high-performance devices, but they are throttled down by body-bias. And so once you detect whatever is going on in the room, you power up the part that you care about. In addition, you have RF integrated on the chip. You send the signal, finish the communications, shut that part back down, and you go back into sleep mode. That’s really optimized for battery-powered applications. The part that’s always on uses ultra-low leakage devices. The other parts use body-bias to turn it on or off.

    Fig. 3: What is body-bias?

    SE: What about 12nm FD-SOI? Why not offer that at 10nm?

    Patton: It’s still planar and we have to go to double patterning. 10nm is a repeat of history on 20nm. 10nm takes things just to the point where you need triple patterning. And so we backed off a little in scaling with a big mask cost reduction. We don’t invoke as many double- or triple-patterning levels. So if you compare it to 10nm, 12nm FD-SOI is 40% less masks. And our 22nm is about 40% less masks than 14nm/16nm.

    SE: There is also a perception that FD-SOI suffers from higher substrate costs. Any thoughts?

    Patton: That’s only part of the equation. When you get a big mask cost savings, you are saving etch steps, deposition steps and others. It compensates for it.

    SE: Let’s move to chip scaling. Is the industry keeping up with scaling or Moore’s Law?

    Patton: It used to be simple. The industry was scaling 50% and would add 10% or 15% complexity for a 30% to 35% die cost improvement. But now you are adding 25% complexity. Let’s just pick that as a number. Now, you are only getting a 20% die cost improvement. That’s not quite as exciting for somebody doing design, especially if you look at the curves on design costs. Design costs have been going up at an exponential rate, so people have to spend more to design in this new technology.

    SE: What about GlobalFoundries’ 7nm technology?

    Patton: Our 7nm is scaled, versus 14nm, about 0.37x. We also know there are more masks than 14nm. At the end of the day, when you take the shrinkage and the complexity increase, we are giving customers a good die cost improvement for the investment they are going to make in the design.

    Fig. 4: Key innovations for 7nm. Source: GlobalFoundries

    SE: GlobalFoundries decided to skip 10nm and move to 7nm. Why?

    Patton: The scaling factor for 10nm is pretty modest. It’s more of a half node. All the things we’ve heard from customers is the performance improvement for 10nm is pretty marginal over the previous node in 16nm/14nm. So for 7nm, if you look at scaling and cost, it’s hitting that cost target of 30% to 35% die cost improvement.

    SE: What are the big challenges for 7nm?

    Patton: Clearly, the complexity is right up there. You are talking about something in the mid-80s for mask count, which is pretty amazing. The middle-of-line is also a key challenging area. Getting to the performance target is the third key challenge.

    SE: For 7nm, GlobalFoundries said it would initially use 193nm immersion and multiple patterning, and not EUV. Is that still the case?

    Patton: Yes, definitely. We have a number of products taping out next year, including the first one in the early part of next year. And EUV is not ready on that time frame. We do have EUV tools coming into Malta. We want to be prepared for the transition because it clearly offers advantages. We have two EUV tools coming in next year, and then we will have another two tools coming in the year after. So we will be well outfitted with EUV tooling. We have our EUV tool, of course, in Albany, which we are using with IBM for development. For manufacturing we will have EUV capability in place. And then we will transition customers and products over to that when it’s ready. It will give us a cycle time and a defect density improvement. And we’ll use it for a shrink on 7nm.

    SE: So you plan to insert EUV at 7nm at some point?

    Patton: We will launch 7nm with immersion. We will make sure our ground rules are compatible in order to migrate levels to EUV. And then, we’ll look at a shrink on that at the right time.

    SE: What about the fins at 7nm? Do you need to make them taller to boost the drive currents?

    Patton: We’ve gone a bit taller with the fins. There are some disadvantages of going to taller fins, as well. The fin shape is probably the most critical one. Getting the fin profile shape is critical. Also, getting that junction isolation is key. Your fin is isolated, but if you get too much overlap to the source-drain, it adds a lot of capacitance. This slows down the transistor.

    SE: Is GlobalFoundries co-developing 7nm technology with Samsung?

    Patton: We are doing it completely on our own. We had the collaboration on 14nm. We still partner with them on what I’d call pathfinding in Albany. As part of the deal with IBM, Albany used to be an all-joint-development alliance. Then it was spilt into two parts. Half of the facility continues to do the joint development work, which IBM leads. Think of that as pathfinding for 5nm and beyond. And the other half is a proprietary IBM-GlobalFoundries corridor, which is specifically focused on accelerating things into Malta. Those could be performance elements for 7nm and 7nm plus. In fact, I would envision we’ll have a bunch of performance kickers at 7nm. This will be a long node.

    SE: So the finFET will last at least until 7nm. What about 5nm?

    Patton: We have work going on that. We have work in new device structures like gate-all-around in Albany. Some think that you can go to 3nm with finFETs. I am a bit skeptical on that topic. We will need some new device structures before then.