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    Reworking Established Nodes


    Attention turns to pre-finFET processes because benefits of device scaling don’t apply equally to all markets.

    New technology markets and a flattening in smartphone growth has sparked a resurgence in older technology processes. For many of these up-and-coming applications, there is no compelling reason to migrate to the latest process node, and equipment companies and fabs are rushing to fill the void.

    As with all electronic devices, the focus is on cost-cutting. But because these markets are likely to generate lower volumes than mobile phones or PCs, the majority of those savings will not come from shrinking features. In many cases, these are either original designs (rather than derivatives), and the technologies are still being developed. Some are custom, some are partially custom, and most are heterogeneous. Designing and manufacturing them using finFET processes would be price-prohibitive.

    At pre-finFET nodes, yield is well established. There are fewer issues such as dynamic power density, RC delay, and thermal effects, and there is no need for multi-patterning. In addition, many of these designs have a high percentage of analog content—or in the case of MEMS chips, mechanical-electrical content—which does not benefit from scaling. The short-term result is a 200mm capacity crisis that may not disappear anytime soon, but the longer-term effect is increased investment in these older nodes.

    “The older established nodes will continue for a long time,” said Walter Ng, vice president of business management at UMC. “The reasons are numerous—overall economics (design cost to silicon cost), proven design support, time to market, and predictability in manufacturing and yield. With the significant cost increase in the most leading edge nodes from a design and manufacturing standpoint, and the cost it takes in volume to drive yields, it is forcing customers to consider more carefully what is the appropriate node for their end application. For most applications, unless you must have the highest levels of performance, there may not be as compelling a business case to focus on the bleeding-edge nodes.”

    In fact, many chipmakers are looking at 28nm—or perhaps 22nm, if there is enough interest—as the end of the scaling roadmap. For some technologies, the current focus may be 130nm or even 250nm. There is a frenzy of activity at all of these nodes, including different materials such as FD-SOI at 28nm and 22nm, different coatings that can change performance and power characteristics, and different power configurations and commercially available and proven IP.

    “Our strategy is to feed forward and feed back,” said Kelvin Low, senior director of foundry marketing at Samsung Foundry. “We are looking at older nodes and hybrid implementations and working to understand future requirements.”

    Low said this is particularly important for power ICs, displays, flash memory and microcontrollers.

    Fig. 1: UMC’s processes and market applications. Source: UMC

    This is reflected in an increased demand both for 200mm capacity, which is now highly constrained, as well as 300mm. Behind all of this are new markets and new ways of approaching existing markets. Apple’s iPhone 7 is a case in point. The application processor was developed on TSMC‘s integrated fan-out process rather than an SoC. But although the logic may be developed at the most advanced node, not every component in that package was developed at the same node. New architectures for automotive, industrial and medical applications, which are heavily reliant on analog sensors, likewise will leverage a mix of components developed at different process nodes and connected over neural networks.

    This shift hasn’t gone unnoticed by foundries, equipment makers and packaging houses. All have introduced a menu of possible options at established nodes, including new materials as well as new process options, including low-power, ultra-low power, high-performance and low-cost options at the same nodes.

    “By using thin films on 200mm you can get higher function but still have low cost,” said Peter Zagvijn, senior technical product manager at ASM. “This is a technology enabler. It will be important for high-voltage electronics and electric cars because it allows you to extend the platform maintainability and the lifetime of the equipment by transferring what happens at the leading edge to the lagging edge. Using ALD technology, there are more than 50 films available for diffusion on one platform.”

    Fig. 2: Extending processes using atomic-layer deposition. Source: ASM.

    Zagvijn said this will be important in wafer-level packaging, as well, which can be a mix of devices developed at different technology nodes. The key here is speeding up the deposition process, which is slower with ALD, because it requires a layer-by-layer application, compared with chemical vapor deposition (CVD) and physical vapor deposition (PVD), which are continuous but less precise.

    More customized solutions
    In one respect, this opens the door to more possible solutions for any engineering problem. But it also increases the number of choices, which can be daunting. Those choices are made even more difficult by the fact that IP varies greatly from one market to the next, and from one foundry to the next.

    “Every time you pick a foundry node, you change the IP ecosystem,” said Mike Gianfagna, vice president of marketing at eSilicon. “There is no one right answer. Do you do a single monolithic chip versus two chips? Do you use a silicon substrate or no substrate? Which IP do you use at which node? This is a highly complex set of decisions.”

    Where possible, though, the emphasis is on reuse rather than new development. Even that isn’t so straightforward. “Selecting IP is only one part of the problem,” said Ranjit Adhikary, vice president of marketing at ClioSoft. “Integrating and using it opens up a whole different set of problems. And if someone is using IP, what problems are they facing? You need a communications channel for what problems are encountered, a methodology flow, documentation, scripts, and a software knowledgebase. This needs to be like Amazon, where you shop around, and if you have questions you check to see if someone else has answered them.”

    In most cases, that kind of infrastructure doesn’t exist. But it is one of the drivers behind the IEEE’s International Roadmap for Devices and Systems (IRDS), which is an attempt to at least add some structure for chips developed for different markets. This stands in stark contrast to IRDS’ predecessor, the International Technology Roadmap for Semiconductors (ITRS), which was focused almost entirely on a timetable for device scaling and identifying where the impediments to progress would be.

    “This is about application domains and markets,” said Tom Conte, co-chair of IEEE’s Rebooting Computing Initiative and a professor of computer science and electrical and computing engineering at Georgia Tech. “There will be competing architectures for different market segments,” Conte said. “So cloud computing includes high-performance computing. IoT edge devices are compute-bound, energy-bound, and have to live within a power envelope. There also are mobile devices, intelligent control systems, which are cyber-physical systems, and feature recognition and media processing.”

    Some of these will likely require different packaging approaches, generally falling into the category of ‘More than Moore.”

    Fig. 3: Different nodes for different markets. Source: TSMC.

    “With each technology forward, the adoption rate gets smaller and smaller. We see that at 14nm, and we will see it more at 7nm and 5nm.” said UMC’s Ng. “We certainly see customers using packaging solutions like multi-chip modules to optimize cost, risk and time-to-market as they leverage silicon from different process technologies and combine into one chip essentially. We also see customers take this approach to reduce board area when the height limitations allow. And we see customers in the performance area who are leveraging more costly approaches in their higher-end products, but wish to find solutions for their mid-and lower-tier products at the right cost/performance benefit. Numerous solutions on the packaging side and silicon side are being considered. Any standardization in this area will come over time, but initially they may be a competitive advantage for those customers that drive the solution and help validate it.”

    That view is being echoed across the semiconductor industry, in large part because some of the new growth markets for chips—regular and industrial IoT, virtual and augmented reality, neural networking, and automotive—can thrive using mainstream process nodes at 45nm and larger. Even those markets that depend on advanced process nodes, such as mobile phones and cloud/enterprise computing, increasingly are becoming heterogeneous mixes of processors and other IP.

    “There are multiple different pieces coming into the picture because the market is so fragmented,” said Ou Li, senior director of engineering at ASE. “So for a new market like the IoT, those devices are relatively cheap. If a device fails, you can replace it. For other markets, that’s not possible. But with devices that are well-proven, we know how to deal with them. It’s the unproven new technologies that are more of a concern.”

    The upshot is that chipmakers want to limit risk in these designs, because that has a direct bearing on cost. One way to accomplish that is to reduce the number of components developed at the most advanced nodes. Even where 10/7nm logic makes sense, it can be surrounded by technology developed at other nodes.

    “At 7nm, the critical dimensions are smaller, so any variation is exacerbated,” said Ruben Molina, product marketing director for timing signoff at Cadence. “At 7nm, the rail voltage approaches the threshold voltage. That creates an increase in sensitivity to variations in a transistor, and it’s more prominent at 7nm and 0.6 volts. The result is a cross-talk effect and substrate noise.”

    Molina said that while advanced packaging adds new challenges, it’s still easier and less expensive to deal with than shrinking features and cramming everything onto one die. “At 7nm, you have to address the density issue and electromigration, which is associated with heat. And it costs a lot of money to equip new fabs at the latest nodes.”

    Rethinking process flows
    There are other ways to cut costs at these older nodes. Microelectromechanical systems (MEMS) devices, which are a combination of mechanical and electrical engineering, are a case in point.

    The problem in the MEMS market is that prices fall faster than economies of scale can be attained, particularly for the commoditized portion of the market that includes accelerometers and gyroscopes. There are two strategies emerging to change that equation. One is to cut costs on the manufacturing side through a more standardized process flow. The second is to add new capabilities into those devices to increase their value.

    “Fully amortized fabs can be repurposed for MEMS,” said Stephen Breit, vice president of engineering at Coventor. “But what’s really needed is a fabless foundry model. This has been talked about for years, and it is finally starting to develop. In CMOS, you send a GDSII layout to the foundry. In MEMS, these are basically handcrafted designs. But people are starting to develop platforms for MEMS plus NEMS processes. You see that with companies like Leti and X-Fab, and also Teledyne DALSA with its MIDIS platform and Invensense with its NF-Shuttle.”

    Breit noted that in the past, companies have tried to create a library of MEMS components, but that met with limited adoption because the schematics need to be in 3D and many MEMS designers don’t have access to EDA tools. “But a lot of MEMS design is implemented as a layout,” he said. “If some of this is sold as IP, you can see how you get from there to a functional model. This requires a custom library, and we have found gaps in the software that will keep us busy for a few years. But established MEMS suppliers also are looking for more sophisticated gyroscopes and pressure sensors, and that will push the need for better modeling capabilities.”

    In effect, this is applying the same kinds of tools that have enabled CMOS-based chips to follow Moore’s Law for the past half century. That kind of cost reduction is essential across many new markets that employ a variety of chips.

    “Health care is 20% of the U.S. economy,” said Jay Esfandyari, senior manager of MEMS product marketing at STMicroelectronics, during a speech at the MEMS and Sensors Technical Congress earlier this month at Stanford University. “Sensor fusion needs to be part of sensor integration. We need the cost and size to decrease, the performance to increase, and we need to reduce the aces of misalignment.”

    Esfandyari said the challenges include:

    • Data collection involving multiple sensors;
    • Lack of availability of very-low-power-technologies
    • The need for faster processing, without increasing power and cost;
    • Multiple and sometimes conflicting communication standards, and
    • Data availability and integrity.

    Even though the cost of the sensors is decreasing, there is a need for more sensors. And for many of the new application areas such as medical, industrial and automotive, they have to be more reliable and more secure—but at the same price point if that reliability and security wasn’t included.

    Not all devices benefit from process shrinks. Passives, such as capacitors, inductors and resistors, and analog components don’t see an improvement in performance by shrinking features. In some cases, shrinking the device can have the opposite effect. And in many cases, it’s simply not cost-effective.

    “It is hard to justify the ROI converting the product into 14nm or 10nm or 7nm unless it has a huge logic die or has large volume,” said UMC’s Ng. “Designs with a significant amount of specialty technology such as eNVM or BCD, it will usually be more cost effective to stay on an older node because the analog or mixed signal portions will not scale as well as the logic, so the die could cost more in a more advanced node. And with so much pressure on corporate margins, selecting one process technology node over another can impact cost of goods one way or another — not just in the silicon cost, but in yield, time to market and predictability/risk. Within foundries there also continue to be considerable development efforts to broaden the support of those established nodes to more end applications.”

    The general perception is that established nodes will stick around for a very long time. As a result, a lot more effort is being put into making those nodes more attractive for chipmakers that cannot justify the additional cost or engineering challenges of moving to the most advanced nodes—or which cannot see enough power/performance/area advantages to scaling devices to the leading edge of physics.