Taiwan Semiconductor Manufacturing Company (TSMC) has announced the initial availability of its Open Innovation Platform Virtual Design Environment (OIP VDE), and the OIP Cloud Alliance.
OIP VDE enables semiconductor customers to securely design in the cloud, leveraging TSMC OIP design infrastructures within the flexibility of cloud infrastructures, according to the foundry house. OIP VDE is the result of TSMC’s collaboration with OIP design ecosystem partners and leading cloud providers to deliver a complete systems-on-chip (SoCs) design environment in the cloud.
With the latest announcement, TSMC’s OIP now consists of five alliances: the EDA Alliance, IP Alliance, Design Center Alliance, Value Chain Aggregator Alliance, and the newest Cloud Alliance. Cloud Alliance members work with TSMC to certify that the capabilities of traditional EDA design flows can be utilized via the cloud.
TSMC made the announcements at its 2018 Open Innovation Platform Ecosystem Forum on October 3.
TSMC said its OIP VDE’s first implementations of digital RTL-to-GDSII and custom schematic capture-to-GDSII flows are via partnerships with TSMC’s inaugural Cloud Alliance partners, Amazon Web Services (AWS), Cadence, Microsoft Azure, and Synopsys.
In TSMC’s enablement of OIP VDE, both digital and custom design flows have been validated in the cloud, along with OIP design collateral – including process technology files, PDKs, foundation IP, and reference flows. To ensure low barriers to entry and high technical support levels, Cadence and Synopsys act as the focal point helping customers to set up VDE and providing first line support.
Microsoft and Cadence collaborated with SiFive, a TSMC IP Alliance partner, to tape out the first full SoC design in TSMC’s OIP VDE. It contained its 64-bit multi-core RISC-V CPU, the Freedom Unleashed 540, which is capable of running a RISC-V Linux distribution and its applications via TSMC OIP VDE. The SiFive implementation was done in the U.S. and India.
Synopsys, a key TSMC IP Alliance, and VDE partner, has successfully taped out its high-speed DesignWare PHY IP for PCI Express 5.0 on TSMC’s advanced 7nm process through the Synopsys Cloud Solution enabled for TSMC OIP VDE using TSMC process models and rule decks. This tapeout, achieved in collaboration with AWS, was accelerated by taking advantage of cloud scalability to 1000+ CPU cores.
Arm, a key TSMC IP Alliance partner, has collaborated with its EDA partners and TSMC, to ensure Arm’s ecosystem of silicon partners are able to immediately design-in-cloud including Arm’s latest processors and across all TSMC nodes through its most advanced 7nm node.
“The cloud is pervasive and will fundamentally influence silicon design. TSMC is the first foundry to collaborate with design ecosystem partners and cloud providers to enable designs in the cloud,” said Cliff Hou, vice president of Technology Development at TSMC. “TSMC OIP VDE provides flexible, secure, and silicon-validated cloud-based design solutions to semiconductor customers, enabling them to optimize and scale their computing infrastructure, and ultimately accelerating time-to-market for next generation SoC designs.”
TSMC OIP VDE is available with the VDE Storefronts being handled directly by Cadence and Synopsys, respectively.
OIP Cloud Alliance
“TSMC is excited to not only adopt the cloud ourselves for our design enablement in TSMC advanced technologies, but also jointly implement OIP Virtual Design Environment, through our collaboration with Cloud Alliance members Amazon Web Services, Cadence, Microsoft Azure, and Synopsys, lowering entry barriers of Cloud adoption for our common customers,” said Hou. “In addition to the requirements of handling large scale SoC batch design activities in the cloud, we have worked with our Cloud Alliance members to ensure that interactive design tasks, such as custom layout, may be performed via hosted environments. This work with our partners further enhances customer productivity by leveraging the flexibility and power of the Cloud, with the traditional Alliance certification that capabilities have been tested with real-world examples.”